1. Field of the Invention
The present invention generally relates to a Low Pin Count (to be abbreviated as LPC hereinafter) device and a method thereof, and more particularly, to a circuit system and a method for data transmission between LPC devices, in which there is an address register installed either in an LPC host controller connected to each LPC device through a respective LPC bus or in each LPC device so that the LPC devices can communicate according to the LPC interface specification.
2. Description of the Prior Art
With the rapid development in the information industry, people have increasing needs for a higher operation speed as well as a higher data transmission rate of information products. The conventional ISA (Industry Standard Architecture) interface is too slow to support the data flow according to the modem electronics products. More particularly, the ISA interface works under the clock frequency of 8 MHz and the number of required pins is 60, which may occupy lots of space and increase the fabrication cost of the socket. Therefore, a new Low Pin Count (LPC) interface is proposed to work under the clock frequency of 33 MHz, which leads to a much higher transmission efficiency, and require only less than 10 pins, which significantly reduce the fabrication cost of the socket. Hence, the LPC interface has received considerable attention.
The circuit system diagram of a conventional LPC circuit system is as shown in FIG. 1, which comprises: an LPC host controller 12, a master LPC device 14, and a slave LPC device 16, wherein the master LPC device 14 and the slave LPC device 16 are connected to the LPC host controller 12 through an LPC bus 18.
According to the LPC interface specification, every cycle of transaction is started and ended by the LPC host controller. Therefore, in the circuit system described above, data transmission is only performed either between the LPC host controller 12 and the master LPC device 14 or between the LPC host controller 12 and the slave LPC device 16, as shown in FIG. 2A and FIG. 2B. FIG. 2A shows the typical timing diagram for the read cycles of the master device, in which LFRAME# is one control line used by the host controller to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. At the beginning of a read cycle, LFRAME# is only normally active at the start of a cycle and the LPC host controller (H) drives a START value on LAD[3:0]. Later, the active device is turned around (TAR) to become the master LPC device (M), which then determines the cycle type and the direction (CYCTYPE+DIR) as a read cycle. Then the address (ADDR) and the size (SIZE) of the data are determined. Later, the active device is turned around (TAR) again to become the LPC host controller (H), which drives a SYNC signal, and responds the data according to the read request of the master LPC device, and then terminate the cycle by an action of turning-around.
FIG. 2B shows the typical timing diagram for the write cycles of the slave device. At the beginning of a write cycle, the LPC host controller (H) drives a START value on LAD[3:0] and then determines the cycle type and the direction (CYCTYPE+DIR) as a write cycle, and further transmits the target address (ADDR) and the data to be written (DATA). Later, the active device is turned around (TAR) to become the slave LPC device (S), which drives a SYNC signal, and writes the data to the address according to the request of the LPC host controller. Finally, turn the bus around to the LPC host controller and terminate the cycle (TAR).
Accordingly, there is no transaction between the master LPC device 14 and the slave LPC device 16. It is a waste of resources that there is no data transmission between devices in the same system. Therefore, there is need in providing a circuit system and method for data transmission between LPC devices so as to simplify the transmission process and increase the transmission efficiency.